Embedded Software Development and Simulation of Processors
If you are developing software for a processor where you do not have access to the hardware or you need a better embedded software development environment – then you probably need to have a look at using a simulator to develop your software on.
The key component in a simulator used for developing embedded software is the CPU model.
This site provides information on the industry’s most comprehensive library of extremely fast and efficient CPU Models of advanced processor cores that work in a variety of simulation environments. The whole focus of these models is to enable you to develop embedded software in a more efficient way, with less bugs, and in less time.
Fast CPU Models
These Fast Processor/CPU Models can be used in C, C++, or SystemC TLM based platforms which you can develop or you can use existing platform models (virtual platforms) available from several sources (e.g. OVP, Imperas). Readily available virtual platform models range from simple bare metal models through to full development board models such as the MIPS Malta or ARM Versatile Express.
All the models have been developed in C using OVP technology and for SystemC TLM have been tested to run with all major SystemC simulators: Cadence, Synopsys, Mentor, Carbon, Accellera/OSCI. The models have also been tested with emulators from Synopsys ZeBu, Cadence Palladium, and Aldec. The models run on both Windows and Linux host platforms. Native OVP simulators (use C platforms) are available from Imperas and OVP.
On this site you will see the scope and variety of the Fast CPU Models available and how easy they are to download and use in C or C++ simulations.
Several companies have downloaded these models and use them within their own internal simulation environments. There are specific APIs to easily allow simulator integration and encapsulation. Cadence working with Imperas is one example.
Largest CPU Model Library in the Industry
Each Fast Processor Model is written in C using the Open Virtual Platforms (OVP) standard public APIs. They include a dedicated native C++ SystemC TLM2 interface provided as source to enable understanding and easy usage. Not only is the specific SystemC TLM2 interface provided as source (click to preview an example), also, the full model is available as source. The models do require a simulator that implements the OVP APIs – such as OVPsim available from OVP, or commercial simulators from companies such as Imperas Software.
There is documentation that explains about the models in general (click to preview) and for each model there is a specific document (click to preview the document for the ARMv8 Cortex-A57MPx4 model) that describes what is available in the model, for example its ports, nets, registers, modes, exceptions, and other configuration/parameter options. On the OVP website there is lot of information about each model (for example click to browse the available information on the ARMv8 Cortex-A57MPx4).
An overview document (click to preview) explains, with the use of examples, how the models are configured and used in SystemC TLM2 platforms.
In a C or C++/SystemC TLM2 environment, the models are used directly, with no inefficient co-simulation. It is very simple to create homogeneous or heterogenous platforms of advanced processor core models. To see examples of platforms ranging from one to twenty-four cores and for platforms that boot full operating systems like Linux and Android, including SMP, visit the the examples and platforms available from the OVP platforms download area or video area.
Many models can be instanced in one platform, virtual platform or virtual system prototype – it is easy to build multi-core multi-processor platforms.
Faster Models means BUGS ARE FOUND SOONER
The models run fast, hundreds of millions of instructions per second (MIPS):
If you need maximum available simulation speed from the Fast CPU Models, then you need to find our more about QuantumLeap from Imperas. This uses the parallel resources of the host PC to accelerate your simulations.
For more information on QuantumLeap parallel simulation acceleration using host resources and to find out how to develop your embedded software at the fastest speeds in the industry, browse the Imperas information.
Fastest Simulation of ARM and MIPS cores
Industry Standard Debug and IDE
Each model supports standard debugging interfaces and can be connected using RSP to GDB, either standalone or within an Eclipse IDE environment. The models also connect to the advanced multi-core debugger available as part of the Imperas Advanced Multicore Software Development Kit product.
Easy to use – watch the video
To see a short video of a Fast CPU Model running in a simple platform – and see it booting to the Linux prompt in under 10 seconds, click the image:
If you want to see other videos, OVP has a collection to view here.
At the top of this page are several menu picks that list the different families and enable access to the model specific information. The listed items on the right provide news related information.
To explore how easy it is to use these Fast CPU Models, look at the OVP starting page.
If you are looking for products to use to develop embedded software visit the Imperas Software website.
Currently available Fast Processor Model Families.